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Instruction set architectures
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61	Adaptive and Reflective Middleware and OS Services for Mobile Applications Managing Power in Dynamic Distributed Environments through cross-layer adaptation Add to Reading List Source URL: mesl.ucsd.edu Language: English - Date: 2009-06-15 02:14:42 Instruction set architectures PowerPC 600 PowerPC Middleware
62	Relaxed memory models must be rigorous ˇ c´ık3 Susmit Sarkar2 Francesco Zappa Nardelli1 Peter Sewell2 Jaroslav Sevˇ Luc Maranget1 Mark Batty2 Jade Alglave1 1 Add to Reading List Source URL: www0.cs.ucl.ac.uk Language: English - Date: 2012-09-10 07:41:00 Instruction set architectures Computer memory X86 architecture X86-64 Java memory model X86 Memory barrier Spinlock Memory ordering Low-level programming language Itanium ARM architecture
63	Chapter 1 Performance Measures Reading: The corresponding chapter in the 2nd edition is Chapter 2, in the 3rd edition it is Chapter 4 and in the 4th edition it is Chapter 1. When selecting a computer, there are differen Add to Reading List Source URL: eceweb.ucsd.edu Language: English - Date: 2015-07-31 19:30:10 Central processing unit Clock signal Computer performance Instruction set architectures Cycles per instruction Rates MIPS instruction set Instructions per second Clock rate CPU time Protection ring Computer
64	PDF Document Add to Reading List Source URL: www.ieee-security.org Language: English - Date: 2015-05-11 16:42:58 Memory management Instruction set architectures Memory protection Capability-based security Kernel Memory management unit MIPS instruction set Protection ring Microkernel EROS Virtual memory 64-bit computing
65	Efficient SIMD Code Generation for Runtime Alignment and Length Conversion Peng Wu Alexandre E. Eichenberger Add to Reading List Source URL: researcher.watson.ibm.com Language: English - Date: 2009-10-23 16:02:22 Computer architecture Assembly languages Parallel computing Instruction set architectures Pointer Data structure alignment SIMD Offset Addressing mode DEC Alpha
66	Advanced Parallel Architecture Annalisa Massini Vector architecture 2 Add to Reading List Source URL: twiki.di.uniroma1.it Language: English - Date: 2015-04-28 17:33:30 Central processing unit Parallel computing Computer architecture Supercomputers Instruction set architectures Processor register Cray-1 MIPS instruction set SIMD Instruction set 64-bit computing Euclidean vector
67	Crackstation Optimised Cryptography On The PlayStation 3 Presented By Nick Breese © 2007 Security-Assessment.com Add to Reading List Source URL: www.security-assessment.com Language: English - Date: 2008-04-11 15:32:18 Instruction set architectures Linux Power Architecture OtherOS PlayStation 3 Cell PlayStation PowerPC Yellow Dog Linux Hypervisor Fedora
68	KVM for IBM z Systems Steffen Thoss z Systems Linux and Virtualization Product Manager Agenda Add to Reading List Source URL: www.susecon.com Language: English - Date: 2015-11-20 12:02:19 IBM zEnterprise System IBM z13 IBM System z Instruction set architectures Linux on z Systems IBM zEC12 Mainframe computer Z/Architecture 45 nanometer
69	Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2015-12-01 06:21:41 Instruction set architectures Central processing unit Computer architecture Memory management Memory protection Capability-based security Pointer MIPS instruction set 64-bit computing Instruction set Reduced instruction set computing Kernel
70	MG_Boilerplate10-WP3b arial Add to Reading List Source URL: www.avant-tek.com Language: English - Date: 2014-07-31 22:34:01 Computer memory System on a chip Embedded microprocessors Instruction set architectures Integrated circuits Application-specific integrated circuit ARC Random-access memory CPU cache Cell

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